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| CS98200 Data Sheet FEATURES s DVD-Video, VCD, VCD 2.0, SVCD, CD, and other popular standards s DVD-Audio including CPPM and VeranceTM watermark protection s MPEG-1, MPEG-2, and leading edge MPEG-4 audio and video decoding s Kodak Picture CD s Flexible ATAPI or AV bus DVD loader support with no additional logic s Dual 32-bit RISC processors, supported by RTOS, C/C++ compilers, and source level debuggers s 32-bit DSP capable of running AC-3, MPEG, DTS, MP3, WMA, and AAC audio decode algorithms s High quality integrated video encoder with six 10-bit video D/A converters s Component (RGB or YUV) or composite & S-Video output s Interlaced (PAL/NTSC) or progressive (480p) output, with Macrovision TM copy protection s CCIR656 video I/O for video capture, PVR and DVR type applications, picture-in-picture support s IEC60958/937 (S/PDIF) & simultaneous PCM output s 5.1 downmix, karaoke echo mix, pitch shift, and many other effects s PAL / NTSC transcoding s Dual 16550 compatible UARTs s ATAPI/ IDE interface for hard disk, audio server, and Personal Video Recorder (PVR) applications s 240-pin MQFP package New Highly-Integrated Processor for Tomorrow's DVD Players and DVD Receivers OVERVIEW CS98200 is a highly-integrated processor that provides all of the audio and video processing functions needed for the next generation of feature-rich DVD players, DVD receivers and Internet DVD applications. Tomorrow's features available today in a single chip solution are DVD-Audio, MP3, WMA(R), MPEG-2/4: AAC, Kodak Picture CDTM, Dolby DigitalTM, Dolby ProLogic IITM, and DTS Digital SurroundTM decoding. It supports most popular CD formats, DVD navigation, disk control, video decoding and up to eight channels of audio output. An extension of Cirrus' CS98000 DVD product line, the CS98200 integrates six 10-bit video digital-to-analog converters (DACs) and TV encoding with progressive scan functionality. Progressive scan video provides high resolution and eliminates the "flickering" effect present in traditional video playback. Other features enabled by this integrated chip include karaoke functionality and video special effects. Its extended feature set makes it ideal for your next innovative DVD application ... today. Need to get your product to market quickly? Cirrus' Total Entertainment platform solutions include DVD front-end controllers, MPEG encoders, audio DSPs, and digital power amplifiers ... everything you need to launch your product before the competition. CS98200 is a Cirrus Total Entertainment Total-ETM IC solution specifically designed for consumer entertainment electronics. (cont.) ORDERING INFORMATION: CS98200-CM See ordering information legend on page 60. Preliminary Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. OCT '02 DS581PP2 1 Copyright 2002 Cirrus Logic (All Rights Reserved) CS98200 Next Generation DVD Processor OVERVIEW (cont.) Here is a summary of the CS98200 features. formats including ATAPI, ISA, and more * I/O channel interface supports all DVD loader protocols System Characteristics * * * * * * Dual 32-bit (180 MHz) RISC processors 32-bit DSP processor ~ 180 MIPS 240-pin MQFP package All I/O pins are 3 V with 5 V tolerance Advanced 0.18 CMOS technology Low power modes and clock shutoff Video Processor * OSD module with multiple regions and transparencies * Full screen graphics module, with 16 bit true-color graphics plane * High quality video scaling using multi-tap programmable vertical and horizontal filters Memory Controller * Up to 120 MHz SDRAM from 4 MB to 32 MB * FLASH databus isolated from SDRAM bus to allow faster SDRAM access * 32-bit data bus for DRAM, 8-bit data bus for ROM data flow engine * Two DMA controllers -- local memory based and direct memory-to-memory * DMA to/from main RAM into local SRAM Video Encoder * Six 10-bit video DAC's, drives 37.5 load directly * Progressive (480p) or interlaced PAL (B, D, G, H, I, N, M, 60) and NTSC mode output * Component (RBG or YUV) or composite + S-Video output * MacrovisionTM 7.1 support (interlaced) and MacrovisionTM 1.03 support (progressive) * Wide-screen signaling support (interlaced and progressive) and CGMS * Closed captioning support MPEG Video Decoder * DVD, VCD, VCD 2.0 and SVCD * MPEG-1, MPEG-2, and MPEG-4 simple profile * Anti-tearing logic controls picture decode and presentation * Advanced error concealment hardware Audio Interface * 8 channels PCM output at 24-bits/192 kHz output rate * 2 channels I2S input at 24-bits/96 kHz * IEC 60958/61937 capabilities External Interface * Serial master/slave ports for controlling DVD device * ATAPI/IDE interface can also control hard disk drives for PVR features * Programmable bidirectional I/O pins * All pins not used for other functions can be reassigned as general purpose I/O pins * Hardware assisted support for infrared remote devices, such as remote control, infrared keyboard, mouse, printer, and more * Programmable parallel host master interface supports 2 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor BLOCK DIAGRAM R IS C 0 R IS C 1 DSP Instruction C ache C PU Pipe D ata C ache MA C Instruction C ache C PU Pipe D ata C ache MA C Instruction C ache X,Y D ata Mem ory Au d io In terfa ce PC M O ut C PU /MA C PC M In SP D IF O ut D V D L o ad er I/O S ys tem C o n tro ls S R AM + C P U IF D VD C ustom Loader Parallel/Serial Data Serial C ontrol H o s t B u s I/O Misc. R egister Banks Tim ers PLL PLL PLL D ata flo w E n g in e 32 K Byte Internal SR A M Arbiter + C ontrol D MA Interrupt AT AP I/G eneric Parallel Bus Interface D MA (R d + W r) FLAS H M em ory.C ontrol S ys tem S yn c N T S C /P AL E n co d er M P E G 4 V id eo D ec o d er Ac ce lera to r D MA (2)t SR A M Buffer D ecryption D igital Encoding 3 D AC s 3 D AC s C PU Interface ALU + logic V id e o P ro ce ss o r ST C Schedule M P E G D ec o d er S u b p ic tu re Line B uffer Video Mixing S im p le I/O VLC Parser R AM Motion C om p ID C T D ual U AR T PW M S em i-D A C 2-W ire Serial (I 2 C ) 3/4 W ire S erial (SP I) Program m able I/O Infrared Input D R AM C o n tro lle r D ecode r Scaler Main V ideo Scaling and D isplay O n Screen D isplay O verlay Picture in P icture O verlay V id e o C ap tu re G rap h ics FIFO D ecoder Line B uffer / F licker F ilter Main G raphics SD R A M C ontrol DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 3 CS98200 Next Generation DVD Processor Table of Contents 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 8 1.1 AC and DC Parametric Specifications ...............................................................................8 1.1.1 Absolute Maximum Rating .................................................................................... 8 1.1.2 Recommended Operating Conditions ...................................................................8 1.1.3 Electrical Characteristics ......................................................................................8 2. TIMINGS .................................................................................................................................. 10 2.1 Timing Diagram Conventions ........................................................................................... 10 2.2 DC Characteristics ........................................................................................................... 11 2.2.1 ATAPI Interface ................................................................................................... 11 2.2.2 DVD Loader Interface ......................................................................................... 12 2.2.3 DVD Serial Interface Timing ................................................................................ 15 2.2.4 SDRAM Interface ................................................................................................ 16 2.2.5 ROM/NVRAM Interface ....................................................................................... 18 2.2.6 Digital Video Output Interface ............................................................................. 20 2.2.7 Video Input Interface ........................................................................................... 21 2.2.8 Audio Input Interface Timing ............................................................................... 22 2.2.9 Audio Output Interface Timing ............................................................................. 23 2.2.10 Miscellaneous Timings ...................................................................................... 24 3. TYPICAL APPLICATION ........................................................................................................ 25 4. CS98200 DEVICE SUMMARY ................................................................................................ 26 4.1 Block Diagram .................................................................................................................. 26 Contacting Cirrus Logic Support Fo r a ll pro du ct qu estio ns a nd in qu iries con tact a C irrus L og ic S ales R e pre se ntative . To find on e n ea rest yo u g o to http://www.cirrus.com /corporate/contacts/sales.cfm IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus" believe that the information contained in ) this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" wit hout warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that info rmation being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this infor mation as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furni hing this information, Cirrus grants no license, s express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or techno logies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDE RSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names i n this document may be trademarks or service marks of their respective owners. 2 Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I C Patent Rights to use those components in a standard I 2C system . HDCD(R), Microsoft(R) and Windows Media TechnologyTM are registered trademarks or trademarks of Microsoft, Inc. in the United States and/or other countries. High Definition Compatible Digital (R) and Pacific MicrosonicsTMInc. are either registered trademarks or trademarks of Pacific Microsonics Inc. in the United States and/or other countries. HDCD technology provided under license from Pacific Microsonics Inc. This products design (and/or software) is covered by one or more of the following: 5,479,168; 5,638,074; 5,640,161; 5,808,574; 5,838,274; 5,854,600; 5,864,311; 5,872,531 with other patents pending. Dolby Digital, AC-3, Dolby Pro Logic, Dolby Pro Logic II, Dolby Surround, Surround EX, Virtual Dolby Digital and the "AAC" logo are trademarks and the "Dolby Digital" logo, "Dolby Digital with Pro Logic II" logo, "Dolby" and the double-"D" symbol are registered trademarks of Dolby Laboratories Licensing Corporation. DTS, DTS Digital Surround, DTS-ES Extended Surround, DTS Neo:6, and DTS Virtual 5.1 are trademarks and the "DTS", "DTS-ES", "DTS Virtual 5.1" logos are registered trademarks of the Digital Theater Systems Corporation. The "MPEG Logo" is a registered trademark of Philips Electronics N. V. Home THX Cinema and THX are registered trademarks of Lucasfilm Ltd. Surround EX is a jointly developed technology of THX and Dolby Labs, Inc. AAC (Advanced Audio Coding) is an "MPEG -2-standard-based" digital audio compression algorithm (offering up 5.1 discrete decoded channels for this implementation) collaboratively developed by AT&T, the Fraunhofer Institute, Dolby Laboratories, and the Sony Corporation. In regards to the MP3 capable functionality of the CS98XXX Family DSP (via downloading of mp3_49 3xxx_vv.ld and mp3e_493xxx_vv.ld application codes) the following statements are applicable: "Supply of this product conveys a license for personal, private andnon-commercial use. MPEG Layer III audio decoding technology licensed from Fraunhofer IIS and THOMSON Multimedia." 4 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 5. 6. 7. 8. 4.2 CS98200 Device Details .................................................................................................. 26 4.2.1 RISC-32 Processors ........................................................................................... 26 4.2.2 Powerful 24/32-Bit DSP ...................................................................................... 26 4.2.3 System Controls .................................................................................................. 26 4.2.4 Memory Controller .............................................................................................. 26 4.2.5 Data Flow Engine ................................................................................................ 27 4.2.6 MPEG Video Decoder ......................................................................................... 27 4.2.7 System Synchronization ..................................................................................... 27 4.2.8 Audio Interface .................................................................................................... 27 4.2.9 Video Input .......................................................................................................... 27 4.2.10 External Interface .............................................................................................. 27 4.2.11 Video Processor ................................................................................................ 27 4.2.12 Sub-Picture Processor ...................................................................................... 27 4.2.13 Graphics Engine ............................................................................................... 27 4.2.14 On Screen Display Module ............................................................................... 28 4.2.15 DVD Loader Interface ....................................................................................... 28 4.2.16 CPU Interface and SRAM Controller ................................................................ 28 4.2.17 Host Bus Interface ............................................................................................ 28 4.2.18 Video Encoder .................................................................................................. 28 4.2.19 System Functions ............................................................................................. 28 FUNCTIONAL DESCRIPTION ............................................................................................... 29 5.1 RISC Processor ............................................................................................................... 29 5.2 DSP Processor ................................................................................................................ 29 5.3 Memory Control ............................................................................................................... 29 5.4 Dataflow Control (DMA) ................................................................................................... 29 5.5 System Control Functions ............................................................................................... 29 5.6 DVD/ATAPI Interface ....................................................................................................... 30 5.7 Serial DVD Interface ........................................................................................................ 30 5.8 MPEG Video Decoding .................................................................................................... 30 5.9 Audio Processing ............................................................................................................. 30 5.10 Video Encoder with Progressive Video DACs ............................................................... 32 5.11 Video Input/Output Interface .......................................................................................... 33 5.12 Universal Asynchronous Receiver/Transmitters (UARTs) ............................................. 34 MEMORY MAP ....................................................................................................................... 35 6.1 Processor Memory Map .................................................................................................. 35 240-PIN MQFP PIN DESCRIPTION ....................................................................................... 36 7.1 240-Pin MQFP Pin Layout ............................................................................................... 36 7.2 240-Pin MQFP Pin Summary .......................................................................................... 37 7.3 Pin Configuration Summary ............................................................................................. 37 7.4 Explanation of Pin Types ................................................................................................. 38 7.5 240-Pin MQFP Pin Assignments ..................................................................................... 38 INTERFACE DESCRIPTIONS ................................................................................................ 49 8.1 SDRAM Interface Pins ..................................................................................................... 49 8.2 ROM/NVRAM Interface Pins ........................................................................................... 49 8.3 Video Output Interface Pins ............................................................................................. 50 8.4 Video Input Interface Pins ............................................................................................... 50 8.5 Audio PCM Interface Pins ............................................................................................... 51 8.6 Host Master/ATAPI Interface ........................................................................................... 52 8.7 DVD Loader Interface ...................................................................................................... 53 8.8 DVD Serial Data Interface ............................................................................................... 53 8.9 SPI Interface .................................................................................................................... 54 8.10 General Purpose Input/Output (GPIO) .......................................................................... 54 8.11 UART Interface Pins ...................................................................................................... 55 8.12 I2C Interface .................................................................................................................. 55 8.13 Miscellaneous Interface Pins ......................................................................................... 55 Copyright 2002 Cirrus Logic (All Rights Reserved) 5 DS581PP2 CS98200 Next Generation DVD Processor 8.14 Power and Ground ......................................................................................................... 56 9. 240-PIN MQFP PACKAGE SPECIFICATIONS ...................................................................... 57 10. CONVENTIONS .................................................................................................................... 58 10.1 Acronyms and Abbreviations ......................................................................................... 58 10.2 Units of Measurement .................................................................................................... 59 10.3 General Conventions ..................................................................................................... 59 10.4 Pin Description Conventions .......................................................................................... 60 11. ORDERING INFORMATION LEGEND ................................................................................. 60 List of Figures Figure 1. Legend for Timing Diagrams .......................................................................................... 10 Figure 2. ATAPI Interface Timing Diagram.................................................................................... 11 Figure 3. DVD Loader Host Interface ............................................................................................ 12 Figure 4. DVD Loader Data Interface ............................................................................................ 13 Figure 5. DVD Loader CD Interface .............................................................................................. 13 Figure 6. DVD Loader CD Interface Formats ................................................................................ 14 Figure 7. DVD Serial Interface Timing ........................................................................................... 15 Figure 8. SDRAM Refresh Transaction ......................................................................................... 16 Figure 9. SDRAM Burst Write Transaction.................................................................................... 16 Figure 10. SDRAM Burst Read Transaction.................................................................................. 17 Figure 11. SDRAM Timing............................................................................................................. 17 Figure 12. ROM/NVRAM Reading Timing ..................................................................................... 18 Figure 13. ROM/NVRAM Write Timing.......................................................................................... 19 Figure 14. CS98200 Digital Video Interface Timing Diagram ........................................................ 20 Figure 15. Video Input Timing ....................................................................................................... 21 Figure 16. Audio Input Timings...................................................................................................... 22 Figure 17. Digital Audio Out Timing Diagram ................................................................................ 23 Figure 18. Miscellaneous Timings ................................................................................................. 24 Figure 19. CS98200 Typical Application ....................................................................................... 25 Figure 20. CS98200 Block Diagram .............................................................................................. 26 Figure 21. Video DAC Connections............................................................................................... 32 Figure 22. UART Data Transfer..................................................................................................... 34 Figure 23. 240-Pin MQFP Pin Layout............................................................................................ 36 Figure 24. 240-Pin MQFP Pinout Summary .................................................................................. 37 Figure 25. 240-Pin MQFP Package Drawing ................................................................................ 57 List of Tables Table 1. ATAPI Interface Characteristics ...................................................................................... 11 Table 2. SDRAM Interface Characteristics.................................................................................... 16 Table 3. RAM/NVROM Characteristics ......................................................................................... 18 Table 4. CS98200 Digital Video Interface Characteristics............................................................. 20 Table 5. Video Input Interface Symbols and Characterization Data .............................................. 21 Table 6. Audio Input Interface Symbols and Characterization Data .............................................. 22 Table 7. Digital Audio Out Characteristics ..................................................................................... 23 Table 8. Miscellaneous Timing Characteristics ............................................................................. 24 Table 9. Memory Map-RISC0 Processor....................................................................................... 35 Table 10. Host Debug Port Address Map...................................................................................... 35 Table 11. DSP Address Map ......................................................................................................... 35 Table 12. Pin Configuration Summary........................................................................................... 37 Table 13. Pin Type Legend ........................................................................................................... 38 Table 14. 240-Pin MQFP Pin Assignments ................................................................................... 38 6 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor Table 15. SDRAM Interface Pins .................................................................................................. 49 Table 16. ROM/NVRAM Interface................................................................................................. 49 Table 17. Video Output Interface .................................................................................................. 50 Table 18. Video Input Interface ..................................................................................................... 50 Table 19. PCM Audio Interface ..................................................................................................... 51 Table 20. Host Master/ATAPI Interface ........................................................................................ 52 Table 21. DVD I/O Channel Interface ........................................................................................... 53 Table 22. SPI Interface ................................................................................................................. 54 Table 23. General Purpose I/O Interface ...................................................................................... 54 Table 24. UART Interface Pins ..................................................................................................... 55 Table 25. I2C Interface Pins .......................................................................................................... 55 Table 26. Miscellaneous Interface Pins ........................................................................................ 55 Table 27. Power and Ground ........................................................................................................ 56 Table 28. Acronyms and Abbreviations ........................................................................................ 58 Table 29. Units of Measurement ................................................................................................... 59 Table 30. Pin Description Conventions ......................................................................................... 60 DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 7 CS98200 Next Generation DVD Processor 1. CHARACTERISTICS AND SPECIFICATIONS 1.1 AC AND DC PARAMETRIC SPECIFICATIONS (AGND, DGND=0 V, all voltages with respect to 0 V) 1.1.1 ABSOLUTE MAXIMUM RATING Symbol VDDIO VDDCORE VI II IO TSOL TVSOL TSTOR TAMB Ptotal Description Power Supply Voltage on analog core and I/O ring Power Supply Voltage on core logic and PLL Digital Input Applied Voltage (power applied) Digital Input Forced Current Digital Output Forced Current Lead Soldering Temperature Vapor Phase Soldering Temperature Storage Temperature (no power applied) Ambient Temperature (power applied) Total Power consumption Min -0,5 -0.5 -0.5 -10 -50 -40 0 Max 4.6 2.5 5.5 10 50 260 235 125 70 2.2 Unit Volts Volts Volts mA mA oC o o o C C C W CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent damage to the device. Cirrus Logic recommends that CS98200 devices operate at the settings described in the next table. 1.1.2 RECOMMENDED OPERATING CONDITIONS Parameter Symbol VIO & VAA VPLL &VDD TAMB Min 3.0 1.62 0 Typ 3.3 1.8 25 Max 3.6 1.98 70 Units Volts Volts o Supply Voltage, Analog and IO Supply Voltage, Core Logic and PLL Ambient Temperature (power applied) C 1.1.3 ELECTRICAL CHARACTERISTICS Parameter Symbol IDD IDD VIH VIL IIN RI VOH VOL IOZ @ buffer rating @ buffer rating VOUT = VSS or VDD RSET = 174 VIN = VDD or VSS Conditions Normal Operating Normal Operating 2.0 -1 2.2 -1 Min Typ 65 210 75 0.8 1 0.4 1 10 MAT Vout RLOAD = 37.53 2 1.28 Max Units mA mA Volts Volts A K Volts Volts A bits % Volts Supply Current, IO Supply Current, Core Logic and PLL Input Voltage, High Input Voltage, Low Input Current Input Pull up/down resistor Output Voltage, High Output Voltage, Low High-Z-state Leakage Video DACs1 DAC Resolution DAC to DAC matching 2 Output Voltage Range 8 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor Differential Gain Differential Phase Signal to Noise Chrominance AM Noise Chrominance PM Noise DG DP SNR AM PM 1 0.5 74 80 75 % % dB dB dB 1.Video parameters guaranteed only with 1% tolerance resistors or better for Rset and RLoad. 2.Only applies to each set of three DACs. 3.RLoad is a double terminated load, which includes a 75 resistor at the video DAC and a 75 resistor at the video monitor. DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 9 CS98200 Next Generation DVD Processor 2. TIMINGS 2.1 Timing Diagram Conventions This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labeled when they occur. Therefore, no additional meaning should be attached unless specifically stated. C lo c k H ig h to Low H ig h /L o w to H ig h Bus Change Bus V a lid U n d e f in e d / I n v a lid V a lid Bus to T r is ta te B u s / S ig n a l O m is s io n Figure 1. Legend for Timing Diagrams 10 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 2.2 DC CHARACTERISTICS (TA= 25 C; VPLL=VDD=1.8V10%, VIO=VAA=3.3 V10%) 2.2.1 ATAPI Interface CS98200 can interface with a ATAPI-type slave loader gluelessly. Figure 2 illustrates a read ATAPI transaction and a write ATAPI transaction. Symbol t t t Description Cycle Time Address Valid to HMRD-/HMWR- Setup 7 Min 87 Typ Max Unit ns ns ns ns ns ns ns ns ns acyc1 aavr ah Address Hold from HMRD-/HMWR Setup 11 H_RD/H_WR Pulse Width H_RD/H_WR Recovery Time H_WR Data Setup H_WR Data Hold H_RD Data Setup H_RD Data hold H_RD Data High-Z-state H_RDY Setup Time H_RDY Hold Time 14 0 63 21 30 8 20 0 8 tarww t t arec awsu tawh t ardsu tarddh t t ardts arsu ns ns ns tarh1 Table 1. ATAPI Interface Characteristics 1.Values are guaranteed by design only tacyc H_A[2:0] , H_CS[3:0] t aavr H_RD/H_WR t arww t ah tarec H_D[15:0](WRITE) tawsu H_D[15:0](READ) tarsu H_RDY(deasserted before tarsu) t arh H_RDY(asserted before tarsu) tardsu t arddh tardts tawh Figure 2. ATAPI Interface Timing Diagram DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 11 CS98200 Next Generation DVD Processor 2.2.2 DVD Loader Interface Symbol tdlckper t t Description DVDL_CK Period DVDL_DI Setup Time DVDL_DI Hold Time DVDL_DO Output Delay from Falling Edge DVD_STB Width DVD_STB Low Time DVD_STB High Time DVD_RDY Output Delay DVD_ENA Setup Time DVD_ENA Hold Time DVD_D[7:0] Setup Time DVD_D[7:0] Hold Time DVD_SOS Setup Time DVD_SOS Hold Time CD_LRCK Setup Time CD_DATA Setup Time CD_DATA Hold Time CD_C2PO Setup Time CD_C2PO Hold Time 5 5 5 5 5 5 5 5 5 5 5 5 Min 400 Typ Max Unit ns ns ns dldisu dldih 10 5 250 40 40 90 tdldod t ns ns % % ns ns ns ns ns ns ns ns ns ns ns ns dlstbwd tdlstbl t t t t dlstbh dlreqod dlensu dlenh tdldsu t t dldh dlsossu tdlsosh t lrcksu tcddsu t t cddh cdcpsu tcdcph D VD L _R DY (Inp ut) tdlckper D VD L -C K (O u tpu t) t dldisu t dldih D VD L _D I (Inp ut) D0 D1 D2 D3 D4 D5 D6 D7 tdldo d D VD L _D O (O u tpu t) D0 D1 D2 D3 D4 D5 D6 D7 Figure 3. DVD Loader Host Interface Copyright 2002 Cirrus Logic (All Rights Reserved) 12 DS581PP2 CS98200 Next Generation DVD Processor td lstbw d D V D _S T B (In p ut) td lre qo d D V D _R E Q (O utp u t) td lstbl t d lstbh t d le nsu D V D _E N A (In p ut) t d le nh t d ld su D V D _D [7:0 ] (In p ut) t d ld h td lso ssu D V D _S O S (In p ut) t d lso sh D V D _E R R (In p ut) Figure 4. DVD Loader Data Interface C D_ B C LK (Inp ut) t lrcksu C D_ L RC K (In p ut) t cddsu tcddh C D_ D A T A (Inp ut) t c2posu t c2poh C D_ C 2P O (Inp ut) Figure 5. DVD Loader CD Interface DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 13 CS98200 Next Generation DVD Processor C D _BC K C D _ LR C K D ATA C 2P0 0 Invalid Left Channel MS B 15 14 13 12 11 10 9 8 LSB 3210 Right Channel MSB 15 14 13 12 11 10 9 8 LS B 3210 7654 Invalid 7654 Lower (Left Channel) Upper (Left Channel) Lower (Right Channel) Upper (Right Channel) 32-bit B CK , MS B First, Rig ht Chan nel L ow, C2P 0 LS B F irst, Da ta latch tim ing high C D _BC K C D _ LR C K D ATA C 2P0 0 Invalid Right Channel MS B 15 14 13 12 11 10 9 8 LSB 3210 Left Channel MSB 15 14 13 12 11 10 9 8 LS B 3210 7654 Invalid 7654 Upper (Right Channel) Lower (Right Channel) Upper (Left Channel) Lower (Left Channel) 32-bit B CK , MS B First, Left C hann el L ow, C2P 0 MS B F irst, Da ta latch tim ing lo w C D _BC K C D _ LR C K D ATA C 2P0 0 Invalid Left Channel MSB 15 14 13 12 11 10 9 8 7 6 5 4 LS B 3210 Right Channel MSB LS B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Left Channel MSB 15 14 13 12 11 10 9 8 Invalid Invalid 765 Upper (Left Channel) Lower (Left Channel) Upper (Right Channel) Lower (Right Channel) Upper (Left Channel) 24-bit B CK , MS B First, Rig ht Chan nel L ow, C 2P 0 M S B F irst, Data la tc h tim ing high C D _BC K C D _ LR C K D ATA C 2P0 0 Invalid Left Channel LSB 012345678 MSB 9 10 11 12 13 14 15 Right Channel LSB 0123 MS B 4 5 6 7 8 9 10 11 12 13 14 15 Left Channel LSB 0 1 2 3 4 5 6 7 8 9 10 Invalid Invalid Upper (Left Channel) Lower (Left Channel) Upper (Right Channel) Lower (Right Channel) Upper (Left Channel) 24-bit B CK , LS B F irst, Right C hann el L ow, C2P 0 MS B F irst, Da ta latch tim ing lo w C D _BC K C D _ LR C K D ATA 0 Invalid Left Channel MSB 15 14 13 12 11 10 9 8 7 6 5 4 LS B 3210 Right Channel MSB LS B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Left Channel MSB 15 14 13 12 11 10 9 8 Invalid Invalid 765 2 4-bit B CK , M S B F irst, R ight C hanne l Low, Da ta latch tim ing high (Note: no C2P 0 for this fo r m at) C D _BC K C D _ LR C K D ATA C 2P0 Right Channel Left Channel Right Channel Left Channel LSB MSB 3 2 1 0 15 14 13 MS B LSB MS B 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7654 LSB MSB LSB MSB 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7654 Lower (Right Channel) Upper (Right Channel) Lower (Left Channel) Upper (Left Channel) Lower (Right Channel) Upper (Right Channel) Lower (Left Channel) Upper (Left Channel) 16-bit B CK , MS B First, Left C hann el L ow, C2P 0 LS B Firs t, Data la tch tim in g high Figure 6. DVD Loader CD Interface Formats 14 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 2.2.3 DVD Serial Interface Timing Symbol tdsckper tdsckl1 tdsckh1 tdsdsu tdsdhd tdscdsu tdscdhd 1 Description DVDS_CLK Period DVDS_CLK Low Time DVDS_CLK High Time DVDS_DATA Setup to DVDS_CLK active edge DVDS_VLD, DVDS_SOS Setup to DVDS_CLK Min 33 40 40 5 5 Typ 50 50 Max Unit ns % % ns ns ns ns DVDS_DATA Hold after DVDS_CLK active edge 5 DVDS_VLD, DVDS_SOS Hold after DVDS_CLK 5 1.Values are guaranteed by design only t dsckper D VD S_C LK (Input) t dsckl t dsckh t dsdsu t dsdhd D VD S_D A TA (Input) t dscdsu D VD S_V LD , D VD S_S O S (Input) t dscdhd Figure 7. DVD Serial Interface Timing DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 15 CS98200 Next Generation DVD Processor 2.2.4 SDRAM Interface CS98200 interfaces with either SDRAM or SGRAM for high data bandwidth transfer. Figure 8 shows the refresh cycle performed by CS98200. Symbol t Description Output Delay from M_CKO active edge M_CKO Period M_D[31:0] delay from M_CKO M_D[31:0] setup to M_CKO M_D[31:0] hold time after M_CKO 3 8 Min Typ 9 Max Unit ns ns mco tmper t t mdow msur 9 ns ns ns tmhr 2.5 Table 2. SDRAM Interface Characteristics M_CKO M_A[10:0] M_BS0_N, M_BS1_N M_RAS_N M_CAS_N M_W E_N M_D[31:0] M_DQM_[3:0] M_AP Figure 8. SDRAM Refresh Transaction M_C KO M_A_[10:0] M_C KE M_R AS _N M_C AS _N M_W E_N M_D [31:0] M_D Q M[3:0] F D0 D1 D2 D3 0 D4 D5 D6 D7 F R0 C0 C1 C2 C3 C4 C5 C6 C7 Figure 9. SDRAM Burst Write Transaction 16 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor M_C KO M_A_[10:0] M_C KE M_R AS _N M_C AS _N M_W E_N M_D [31:0] M_D Q M[3:0] F D0 0 D1 D2 D3 D4 D5 D6 F D7 R0 C0 C1 C2 C3 C4 C5 C6 C7 Figure 10. SDRAM Burst Read Transaction tmco M_CKO M_RAS_N,M_CAS_N M_WE_N,M_AP,M_DQM[3:0], M_CKE,M_A[10:0] M_D[31:0](WRITE) tmper tmdow M_D[31:0](READ) tmsur tmhr Figure 11. SDRAM Timing DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 17 CS98200 Next Generation DVD Processor 2.2.5 ROM/NVRAM Interface Symbol trc t t Description Read Cycle Time CE to Data Setup OE to Data Setup Address to Data Setup Address to WE setup (Write) CE to WE setup (Write) WE Pulse Width (Write) CE to Data Output (Write) WE to Data Hold (Write) Min 75 Typ Max 80 70 80 Unit ns ns ns ns ns ns ns cds ods tads t aws 64 64 160 0 10 tcws t t wp cdo ns ns tdh Table 3. RAM/NVROM Characteristics t rc Address[22:0] NV_CE_N tcds NV_O E_N (M _AP) tods tads M _D[7:0] NV_W E_N Figure 12. ROM/NVRAM Reading Timing 18 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor t aw s A d d r[2 2 :0 ] N V_C E _N t cws N V_W E_N tw p t cdo M _ D [7 :0 ] N V_O E_N (M _ A P ) tw dh Figure 13. ROM/NVRAM Write Timing DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 19 CS98200 Next Generation DVD Processor 2.2.6 Digital Video Output Interface Figure 14 illustrates the signal timing for the digital video interface pins. Symbol tvocper1 t t Description XTLCLK period VDAT[7:0] delay from XTLCLK Vsync/Hsync delay from XTLCLK Min -10 -10 Typ 37.037 Max 10 10 Unit ns ns ns covo12 covo22 Table 4. CS98200 Digital Video Interface Characteristics 1.Values are guaranteed by design only 2.It is recommanded that the output data should be taken at the opposite edge of the CLK27_O. t vocper V o ut_ C LK (O utp ut) t covo1 V o ut_ D 7:0 ] (O utp ut) t covo2 V o ut_ H S /V ou t_V S (O utp ut) Figure 14. CS98200 Digital Video Interface Timing Diagram 20 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 2.2.7 Symbol tvicper tsutc1 thvi tsutc2 Video Input Interface Description Video Clock input period VIN_D[7:0] setup time VIN_D[7:0] hold time VIN_HS/VS setup time 5 5 5 Min Typ 37.037 Max Unit ns ns ns ns Table 5. Video Input Interface Symbols and Characterization Data . t vicper V IN _C LK t sutc1 V IN _D [7-0] t sutc2 V IN _H S ,V IN _VS t hvi Figure 15. Video Input Timing DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 21 CS98200 Next Generation DVD Processor 2.2.8 Symbol taicl taich taiper tlrts tsdsus tsdhs Audio Input Interface Timing Description AUDI_BCK Low Time1, 2 AUDI_BCK High Time 1, 2 AUDI_BCK period1, 2 AUDI_LR setup time AUDI_D setup time AUDI_D hold time Min 40 40 80 5 5 5 Typ 50 50 Max Units % % ns ns ns ns Table 6. Audio Input Interface Symbols and Characterization Data 1.Values are guaranteed by design only 2.Active clock edge is programmable. Timing is referenced from active edge t aiper t aich AUDI_BCK (Input) t aicl t lrts AUDI_LRCK (Input) t sdsus t sdhs AUDI_DATA (Input) Figure 16. Audio Input Timings 22 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 2.2.9 Audio Output Interface Timing Figure 17 and Figure 16 illustrate the signal timing for the digital audio pins. Symbol taxper taxch taxcl tsdmo tsdmi taoper tlrds tadsm Description AUD_XCLK period (Input/Output)1, 2 AUD_XCLK High Time (Input/Output)1, 2 AUD_XCLK Low Time (Input/Output)1, 2 AUDO_BCK delay from AUD_XCLK output rise AUDO_BCK delay from AUD_XCLK input rise AUDO_BCK period (Output)1, 2 AUDO_LR delay from AUDO_BCK output rise 104 -10 10 10 ns ns Min 13 40 47 50 50 10 20 Typ Max Unit ns % % AUDO_D[3:0] delay from AUDO_BCK output rise -10 Table 7. Digital Audio Out Characteristics 1.Values are guaranteed by design only 2.Active clock edge is programmable. Timing is referenced from active edge t AUD_XCLK(Input/Output) t AUDO_BCK(Output) t sdm axch axper t axcl t aoperl AUDO_BCK(Output) t AUDO_LR(Output) t adsm AUDO_DO[3:0] (Output) lrds Figure 17. Digital Audio Out Timing Diagram DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 23 CS98200 Next Generation DVD Processor 2.2.10 Miscellaneous Timings Symbol txccper1 t t Description XTLCLK period RST_N Low Pulse Width GPIO PW High GPIO PW Low Min 1000 50 50 Typ 37.037 Max Unit ns ns ns ns rstl gph tgpl Table 8. Miscellaneous Timing Characteristics 1.XTLCLK must meet the requirement of external the video encoder for correct chroma (27 MHz 1 KHz). t xccper XTLCLOCK trstl RESET-N tgph tgpl GPIO Figure 18. Miscellaneous Timings 24 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 3. TYPICAL APPLICATION The Figure 19 shows a typical example of a complete DVD Receiver solution using the CS98200. Rem ote .. K eybo ard . . Con trol F ro n t P a n e l IR D ig ita l In te rf a c e R e c e iv e r (4 )A u d io DACs S /P D IF In pu t A u dio-L(4 ) A u dio-R(4 ) A u dio u p to 8 C ha nn els A u dio-L A u dio-R V ide o A u d io ADC V id e o D eco der C S 9 82 00 S /P D IF O utpu t S -V ide o C o m po site V ide o FL ASH SDRAM 8M (U p to 3 2 M B) 6 V id eo DA C s CD L oad er (A T A P I , A /V ) 2M (U p to 8 M B) C o m po nen t V id eo Po w er R eg . S w itch P o w er Figure 19. CS98200 Typical Application DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 25 CS98200 Next Generation DVD Processor 4. CS98200 DEVICE SUMMARY 4.1 Block Diagram The CS98200 block diagram is shown in Figure 20. RISC1 (Application) RISC0 ADDR MPEG2 Video Decoder SubPicture Decoder (Navigation and Control) DATA PLL (Main, Audio, SDRAM) PCM, SPDIF Interface 2/4/8/16 Bit OSD t Video Processor (I/O, Scale, PIP, Mix) Host Interface AUDIO DSP DMA Control (BitBlt, CSS) (ATAPI,AV,ISA) External IO (GPIO, IR) Graphics Mem Control (SDRAM,ROM) Registers Figure 20. CS98200 Block Diagram 4.2 4.2.1 CS98200 Device Details RISC-32 Processors * Two Powerful 32-bit RISC processors (RISC0 and RISC1), Generation III * Virtual memory support * Optimizing C compiler * Big or little endian data formats support * MAC multiply/accumulate in 2 cycles with C support * 4 Kbyte instruction cache, 2 Kbyte data cache * Single cycle instructions, runs at 180 Mhz 4.2.2 Powerful 24/32-Bit DSP * Expanded 4 Kbyte X + 16 KByte Y paged program visible local memory, Total data RAM = 20 KBytes 4.2.3 System Controls * Powerful 24/32-bit DSP processor * 24-bit fixed point logic, with 54-bit accumulator * Single-cycle throughput, 2-cycle latency multiply accumulate, 32-bit simple integer logic. 8-Kbyte instruction cache * Single cycle instructions, runs at 180 Mhz 26 * Includes several hardware lockable semaphore registers * General-purpose register for inter-processor communication * 32-bit timers for I/O and other uses, with programmable interval rates * Both hardware and software interrupts on data or debug * Built in PLLs generate all required clocks from 27 Mhz input clock 4.2.4 Memory Controller * Supports standard SDRAM and SGRAM, 32-bit data mode only, from 4 MByte to 32 MByte * Includes a separate dedicated DRAM clock, so memory can run asynchronous to the system clock DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) CS98200 Next Generation DVD Processor * High speed, can handle up to 120 MHz DRAM speeds * Supports 8-bit parallel ROM or FLASH, up to 8 MB * Single bank of SDRAM only. Single bank of ROM/FLASH only * Separate data bus for ROM, reduces loading for improved speed, Also handles 5 V easier. 4.2.5 Data Flow Engine 4.2.9 Video Input * NTSC/PAL video decoder input interface * Video input image can be displayed in small window, or as main picture 4.2.10 * 2432 bytes of internal memory * DMA to/from main RAM into local SRAM * Supports endian conversion and byte, short, long data formats on DMA * Supports block transfers for graphics bit blits 4.2.6 MPEG Video Decoder * * 29 independent fully programmable bi-directional I/O pins * 8 edge or level detection interrupt pins * Hardware assisted support for infrared remote devices, such as remote control, infrared keyboard * Dual UART 4.2.11 Video Processor External Interface Serial I2C(R) master and slave port * Supports VCD, VCD 2.0, DVD video standards * Supports trick features, including smooth 2x play and reverse play * Special anti-tearing logic controls picture decode and presentation * Advanced error concealment hardware * New acceleration modules for MPEG-4 Simple Profiles support 4.2.7 System Synchronization * System time clock (STC) for audio/video synchronization * Flexible interrupt structure for controlling decode and presentation times * Hardware scheduling of subpicture and highlight events 4.2.8 Audio Interface * Supports 8 channels PCM output at up to 24 bits and 192 kHz output rate. * Supports 2 channels I2S input at up to 24 bits and 96 kHz input rate. * Simultaneous IEC-958 (SPDIF) output with programmable channel status and user data. * SPDIF, PCM input, and PCM output can all have different XCLK dividers. * Supports simultaneous 192 Khz front and 96 Khz surround, for DVD audio DS581PP2 * Supports 24-bit 4:2:0 and 4:2:2 video modes and 16-bit true color graphics modes. * Picture-in-picture module includes horizontal and vertical downscaling with programmable output sizes, positions, and borders * Overlay mixer with RGB to YUV conversion and output formatting * Supports 4:2:0, 4:2:2, YUV655, RGB565 and RGB555 frame buffer inputs * Outputs 4:2:2 video in CCIR-601 or CCIR656 format * High quality scaling using a vertical and a horizontal 16 taps polyphase programmable filter and supports any size image up to 768x576 * 3 taps adaptative anti-flicker filtering * Master or Slave video sync configuration * Multiple video plains overlay (main video / video input / picture_in_picture / picture/on-screen / display) * Gamma correction 4.2.12 Sub-Picture Processor * Run-length decode DVD sub-pictures * Hardware vertical scaling supports NTSCPAL format conversion * 16-level alpha blending 4.2.13 Graphics Engine * 16 bit true color * Progressive and interlaced mode support 27 Copyright 2002 Cirrus Logic (All Rights Reserved) CS98200 Next Generation DVD Processor * * * * Supports gamma correction Color-key type transparency support Global blending support Frame buffer wrap around support for scrolling * 3 tap horizontal and vertical filtering 4.2.14 On Screen Display Module Macrovision 1.03 support (progressive) * Wide-screen signalling support (interlaced and progressive) and CGMS support * Closed captioning support 4.2.19 System Functions * Supports 2-bit and 4-bit pixel modes * 3 separate regions support * 16 transparency overlay levels support 4.2.15 DVD Loader Interface * * * * * 240-pin MQFP package All I/O pins are 3 V with 5V tolerance Advanced 0.18 micron CMOS technology Internal processors run at 180 MHz Supports Low Power modes and clock shutoff * 4-pin serial interface to low-cost DVD loaders * Loader control via separate 2-wire serial master control port * IO channel interface supports standard 8 bit DVD loader protocols 4.2.16 CPU Interface and SRAM Controller * Internal SRAM of 32 KByte, and controller, synchronous with the CPUs at 180 Mhz * Fast interfaces to RISCs and DSP * Asynchronous interfaces to the main system clock * Special DMA engine, with multiple software clients, and command FIFO * Special interface to MPEG-4 video module 4.2.17 Host Bus Interface * Programmable parallel host master interface supports formats including ATAPI, ISA, and more * Internal DMA module, for I/O type reads and writes on the host bus * Extra chip selects, for more external devices 4.2.18 Video Encoder * Six 10-bit video DACs, drive 37.5 W load directly without external buffering * Supports PAL (B, D, G, H, I, N, M, 60) and NTSC * Component (RBG or YUV) or composite + SVideo output * Progressive or interlaced mode output * Macrovision 7.1 support (interlaced) and 28 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 5. FUNCTIONAL DESCRIPTION 5.1 RISC Processor The CS98200 includes two powerful, third-generation proprietary 32-bit RISC processors, RISC0 and RISC1, with optimizing C compiler support and source level debugger. The RISC processors fully support many Real Time Operation Systems (RTOS). The DVD application user interface resides on RISC1 and is customer programmable. The real time control of low level DVD functions is performed by RISC0. RISC1 gains access to system resources controlled by RISC0 via calls through an Applications Programming Interface, See the CS98200 Software API. All RISC0 firmware, API and sample application code are supplied with the CS98200. The RISC processors also have a MAC engine, which performs multiply/accumulate in 2 cycles in a pipelined fashion with C support, effectively achieving single cycle throughout. The RISC0 processor coordinates on-chip multithreaded tasks, as well as system activities such as remote control and front panel control. The DVD application end-user interface resides on RISC1, and any modifications to that interface occur through the CS98200 API. 5.2 DSP Processor The CS98200 contains a proprietary digital signal processor (DSP), which is optimized for audio applications. The DSP performs 32-bit simple integer operations, and has a 24-bit fixed point logic unit, with a 54-bit accumulator. The multiply-accumulator has single-cycle throughput, with two cycle latency. The DSP is optimized for bit packing and unpacking operations. The interface to main memory is designed for handling flexible block sizes and skip counts. 5.3 Memory Control The DRAM Interface performs the SDRAM control and arbitration functions for all the other modules in the CS98200. The DRAM interface DS581PP2 services and arbitrates a number of clients and stores their code and/or data within the local memory. This arbitration and scheduling guarantees the allocation of sufficient bandwidth to the various clients. The DRAM Interface supports up to 32 Mbytes. For a typical DVD player application, CS98200 requires 8 Mbytes memory space. Sharing the same interface, CS98200 also supports FLASH ROM, OTP, or mask ROM interface. Code is stored in ROM. After the system is booted, the code is shadowed inside SDRAM for execution. The FLASH ROM interface is provided so that the code can be upgraded in the field once the communications channel is established. Utility software will be provided to debug and upgrade code for the system manufacturer. 5.4 Dataflow Control (DMA) The DMA controller moves data between the external memory and internal memory. The external memory address can be specified using a register, or in FIFO mode, using start and end address registers. Separate start/end address registers are used for DMA read and write operations. The DMA interface also has a block transfer function, which allows for the transfer of one block of data from one external memory location to another external memory location. In effect, this feature combines a DMA read and write into one operation. In addition, the DMA write operation allows for byte, short, word, and other types of masking. 5.5 System Control Functions The system control functions are used to coordinate the activities of the multiple processors, and to provide the supporting system operations. Eight 32-bit communication registers are available for inter-processor communication, and 32 semaphore registers are used for resource locking. Timers are available for generalpurpose functions, as well as more specialized 29 Copyright 2002 Cirrus Logic (All Rights Reserved) CS98200 Next Generation DVD Processor functions such as watchdog timers and performance monitoring. The large number of general purpose I/Os offers flexibility in system configurations. An I2C master allows for control of other I2C devices, such as a video encoder. An I2C slave port shares the same pins, and can be used for debug functions. Interrupts can be generated on specific or generic events. Infrared inputs can be filtered to make them free of glitches or stored unfiltered into memory. Control of all the internal clocks is also possible. There are two separate PLLs that are clocked by the 27 MHz clock input. One PLL generates the main clock and DRAM interface clock, and the second generates the Audio 256X/384X clock. 5.6 DVD/ATAPI Interface The CS98200 has a programmable interface port which can be configured to connect to industry standard CD/DVD loaders without external glue logic. The CD/DVD interface fully supports many popular CD/DVD loaders. The interface consists of DVD control and data ports and an optional CD control/data port. The CS98200 hardware manages the DVD interface and moving data to an arbitrary size input FIFO in DRAM. The same interface pins can be optionally configured as a generic 16-bit host master port. In this mode, the CS98200 can control up to four devices (using 4 chip select outputs), each of which may use different protocol and timing. The interface can be set up in ATAPI mode, to connect directly to any ATAPI DVD loader (using two chip selects). Simultaneously, the other two chip selects can be configured to connect to other devices, such as a super I/O chip or hard disk. A third option is to configure the interface for micro-less DVD loader operation, which may also be configured to connect without external glue logic. 5.7 Serial DVD Interface The CS98200 has a 4-pin serial port which interfaces to the data port of popular low-cost DVD loaders. This type of loader provides for low system cost by eliminating the track buffer, interface FIFO, and flow control logic. The CS98200 contains a large internal SRAM to handle high burst data rates, without requiring reverse flow control. The CS98200 performs error detection, sector number tracking, and interrupt generation. 5.8 MPEG Video Decoding Compressed MPEG data is read from the DVD disk into an input FIFO in DRAM. The data flow (DMA) controller moves Video packets from the input FIFO into the MPEG decoder's input FIFO (also in DRAM). The DMA controller can also perform advanced functions such as start code search, relieving the RISC processors. The System Synchronization function is used to control the timing of MPEG picture decoding. The MPEG Video decoder processes I, B, and P frames, and writes to video frame buffers in DRAM for output to the display. Special antitearing logic ensures that currently displayed frame buffers are not overwritten. 5.9 Audio Processing Compressed Audio data is read from the DVD disk into an input FIFO in DRAM. The data is decompressed, then written to a PCM output FIFO, also in DRAM. Presentation time stamps (PTS) are extracted from the stream to update the STC, in order to maintain audio/video synchronization. The DMA and decompression stages of audio processing can be done with a combination of the DMA unit, DSP, and RISC processors. The DSP is optimized for audio processing, so most common formats can be handled by the DSP alone, including AC-3, DTS, MPEG2 audio, and MP3. The DSP has enough reserve bandwidth 30 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor to handle the Karaoke echo-mix and pitch shift, and AC-3 down-mix functions. The audio output data is written into a DRAM FIFO in 16-, 18-, 20- or 24-bit PCM format. A flexible audio output stage can simultaneously output 8 channels of PCM data to audio DACs up to 192 KHz sample rate, plus an IEC-958 encoded output at up to 48 KHz. The audio interface also includes a flexible audio input interface, which can input a wide range of protocols from an audio ADC or an IEC-958 receiver at up to 96 KHz. DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 31 CS98200 Next Generation DVD Processor 5.10 Video Encoder with Progressive Video DACs The CS98200 incorporates an enhanced video encoder with six 10-bit video DACs that drive double terminated 75 directly without external buffering. These termination resistors should be located as close as possible to the CS98200. All analog video outputs should be connected through filters to video connectors (TV/Monitor). The video filters should be located as close as possible to the video connectors. Two schottky diodes should be connected to each output in order to protect the CS98200 from surges caused by being connected and disconnected to the external devices. Figure 21 shows the video DAC connections. Six 10-bit DACs provide two channels for an SVideo output port, one composite video output, and three RGB or Y, Pb, Pr outputs. Video output can be formatted to be compatible with NTSC (M,J), PAL (B, D, G, H, I, M, 60), and 480P. The video encoder is compliant with both Macrovision 7.1 for the interlaced video (NTSC, PAL) and 1.03 for the progressive scan (480p). The video encoder also supports WSS (WideScreen Signaling), CGMS (Copy Generation Management System), and Closed Caption. 3 .3 V 0 .0 1 u F CO M P 1&2 RSE T 1&2 VRE F 1& 2 0 .0 1 u F 10uF 174 1% 22pF Y 1 .8 u H 75 1% 270pF 330pF Yout V i d o e F il te r CS98200 C V id e o F ilt e r C out CV V id e o F ilt e r CV out VR V id e o F ilt e r VR out YG V id e o F ilt e r YG out UB V id e o F ilt e r UB out Figure 21. Video DAC Connections 32 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 5.11 Video Input/Output Interface In addition to the six 10-bit video DACs, the CS98200 provides a separate Digital Video Interface that will give you flexible and powerful means of outputting digital video data to external devices in CCIR601/3 and CCIR656 formats. The interface directly supports NTSC/PAL video encoding, in both master and slave synchronization configurations. The internal frame buffer format could be 4:2:0, 4:2:2, YUV655, RGB565 and RGB555. The CS98200 also features an NTSC/PAL video decoder input interface. The interface accepts CCIR601, CIF, and QCIF formats, out of many TV decoders on the market. The video processor also allows overlay of multiple video planes (main video / video input / picture_in_picture / on-screen display). The Video Input Scaler (VIS) module inputs 8bit digital video data from a camera or PAL/NTSC decoder and simply dump all the data to DRAM. The scaled image, with a border, can be overlaid anywhere on the screen into a 1/2 or 1/4-screen sized window by the Picture in Picture (PIP) module. An alternate method of using the Video Input function is to input a full sized picture and present it on the screen full size (bypass mode). In this mode, the PIP module can place full motion DVD images in the small window. An internal glitch-free mux can switch the video processor clock source from the internal clock to the Video Input clock, allowing the PIP mode to switch back and forth on the fly, with no dropout. DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 33 CS98200 Next Generation DVD Processor Universal Asynchronous Receiver/Transmitters (UARTs) The UART performs serial-to-parallel conversion on data characters received from a peripheral device and parallel-to-serial conversion on data characters received from the host processor. Figure 22 shows RXD and TXD data transfers over the UART interface. The CS98200 has 2 UART interfaces based on a NS16550-compatible design, which incorporates 16-byte transmit and receive FIFOs to enhance performance and throughput. As with the 16650, it can operate in both FIFO-mode (16550) or in the original non-FIFO mode (16450). The main registers are identical in structure to the NS16550, but some unused bits have been enabled for added functionality. The standard features are: * Compatible with 16450 UART * 16-byte transmit and receive FIFOs reduce number of interrupts presented to CPU * Generates and detects standard asynchronous communication bits (start, stop and parity) to and from serial data * Independently controlled transmit, receive, line status and data set interrupts * Programmable baud rate generator (16 bit divisor) 5.12 * Modem control interface (CTS, RTS, DSR, DTR, RI and DCD) * Fully programmable serial-interface characteristics: -- 5, 6, 7 or 8 bit characters -- Even, odd or no-parity bit generation/detection -- 1, 11/2, or 2 stop bit generation * * * * * * * * False start bit detection Complete status reporting capabilities Line break generation and detection Internal loopback diagnostic mode Programmable trigger levels for FIFOs Selectable DMA signaling mode Prioritized interrupts Transmitter and receiver FIFO time-out interrupts Additional optimizations: * Byte enable register allows transfer of up to 4 bytes in a single register write (only in FIFO mode). * External loopback diagnostic mode * Separate baud clock input available * Additional receiver error information Note: If using separate baud clock, it must be less than 1/2 frequency of the system clock, otherwise, you must use the system clock. RXD S ta rt D a ta B its (5 ~ 8 ) P a rity S to p TXD S ta rt D a ta B its (5 ~ 8 ) P a rity S to p S ta rt Figure 22. UART Data Transfer 34 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 6. MEMORY MAP 6.1 Processor Memory Map The CS98200 externally supports up to 32 Mbytes DRAM and 16 Mbytes ROM/NVRAM. Table 9, Table 10, and Table 11 on the next page list the memory map as viewed by the RISC processors, and identifies whether each segment is mapped or cacheable. For detailed information on programming CS98200 memory, see CS98200 Memory Interface User's Manual (DS525UMD1). Address Description Cached 0x8000_0000 - 0x8000_7FFF 0x8200_0000 - 0x83FF_FFFF 0x9400_0000 - 0x97FF_FFFF 0x9800_0000 - 0x9BFF_FFFF 0x9C00_0000 - 0x9FFF_FFFF 0xA000_0000 - 0xA000_7FFF 0xA200_0000 - 0xA3FF_FFFF 0xB000_0000 - 0xB003_FFFF 0xB400_0000 - 0xB7FF_FFFF 0xB800_0000 - 0xBBFF_FFFF 0xBC00_0000 - 0xBFFF_FFFF Internal SRAM (32 Kbytes) External DRAM (32 Mbytes) External DRAM w/ Dcache flush (32 Mbytes) External ROM/NVRAM read/write (16 Mbytes) External ROM/NVRAM read only (16 Mbytes) Internal SRAM (32 Kbytes) External DRAM (32 Mbytes) Internal registers and SRAMs External DRAM w/ Dcache flush (32 Mbytes) External ROM/NVRAM read/write (16 Mbytes) External ROM/NVRAM read only (16 Mbytes) Yes Yes Yes Yes Yes No No No No No No Table 9. Memory Map-RISC0 Processor Host Byte Address 0x0000_0000 - 0x0003_FFFF 0x1000_0000 - 0x11FF_FFFF 0x1200_0000 - 0x13FF_FFF 0x1400_0000 - 0x14FF_FFFF Description Internal registers and SRAMs External DRAM (32 Mbytes) Internal SRAM External ROM/NVRAM space (16 Mbytes) Table 10. Host Debug Port Address Map Byte Address Offset 0x0000_0000 - 0x0003_FFFF (I/O space) 0x0000_0000 - 0x01FF_FFFF (memory space) 0x0200_0000 - 0x0200_7FFF (memory space) Description Internal Registers and SRAMs External DRAM (32 Mbytes) Internal SRAM (32 Kbytes) Table 11. DSP Address Map DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 35 CS98200 Next Generation DVD Processor 7. 240-PIN MQFP PIN DESCRIPTION 7.1 240-Pin MQFP Pin Layout Figure 23 shows the layout of all the pins for the 240-pin MQFP package. The direction of the arrow by each pin shows whether the pin is an input, output, or bidirectional. 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 P LL_1V 8 D VD_D_3 D VD_D_2 H _ALE H _A_3 DVD_D_1 D VD _D_0 H _A_2 H _A_1 D IG_G ND H _A_0 D IG_1V8 D VDL_RDY D AC_A3V3 D AC_A3V3 D AC_AGN D D AC_A3V3 D AC_AGN D V REF1 ISET1 C OMP 1 D AC_AGN D D AC_A3V3 C V_OUT D AC_AGN D D AC_A3V3 Y _O UT D AC_AGN D D AC_A3V3 C _OUT D AC_DG ND D AC_D1V8 D AC_AGN D C D_C2P0 C D_DATA C D_LRCK C D_BCLK H _D_15 H _D_14 H _D_13 H _D_12 H _D_11 H _D_10 H _D_9 H _D_8 H _D_7 H _D_6 H _D_5 IO_GN D V IN_CLK IO_3V3 V IN_HS V IN_VS H _D_4 H _D_3 H _D_2 H _D_1 H _D_0 IO_GN D P LL_1V 8 36 PLL_1V8 RST_N TEST IR_IN CD C_CLK CDC_SYNC C DC _SD O C D C_S D I IO_3V3 M_DQ M_3 M_D_31 M_D_30 M_D_29 IO_G ND M_D_28 M_D_27 M_D_26 M_D_25 IO_3V3 M_D_24 M_D_23 DIG_1V8 M_D_22 D IG_G ND IO_G ND M_D_21 M_D_20 M_D_19 M_D_18 M_D_17 IO_3V3 M_D_16 M_DQ M_2 IO_G ND M_DQ M_1 M_D_15 M_D_14 M_D_13 M_D_12 M_D_11 IO_3V3 M_D_10 IO_G ND D IG_G ND M_D_9 DIG_1V8 M_D_8 M_D_7 M_D_6 M_D_5 M_D_4 IO_G ND M_D_3 IO_3V3 M_D_2 M_D_1 VIN_D_0 VIN_D_1 VIN_D_2 VIN_D_3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PLL_GN D DVD _D_4 DVD _D_5 DVD _D_6 DVD _D_7 H_CS_0 H_CS_1 IO _3V3 H_C S_2 IO_GN D H_C S_3 H_R D H_W R H_RD Y SPI_C LK S PI_DO SP I_DI S PI_RD Y A UDI_D A UDI_LR AU DI_BC K DA C_AGN D DAC_D 1V8 DA C_DGN D UB_OU T DAC _A3V3 DA C_AGN D YG_OU T DAC _A3V3 DA C_AGN D VR_OU T DAC _A3V3 DA C_AGN D COM P2 IS ET2 VR EF2 DA C_AGN D DAC _A3V3 DA C_AGN D DAC _A3V3 DAC _A3V3 AUDO _LR DIG _1V8 AU DO_BC K DIG_GN D AUD_XC LK AUDO _D_1 AUDO _D_2 AUDO _D_3 IO _3V3 XTLCLK_I XTLCLK_O IO_GN D AUDO _D_0 S PDIF_O DVD_S TB DVD_EN A DVD_SO S DVD_ER R PLL_GN D 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 CS98200 240-Pin MQFP 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PLL_1V8 DV DL_CK DV DL_DO DV DL_DI DV D_RDY PW M_O RX D_2 TXD _2 RX D_1 TXD _1 SD A2 SC L2 SD A1 SC L1 VIN_D_7 IO_3V3 VIN_D_6 VIN_D_5 VIN_D_4 NV _D_7 DIG_1V8 NV _D_6 DIG_G ND IO_GN D NV _D_5 NV _D_4 NV _D_3 NV _D_2 NV _D_1 NV _D_0 M _A_0 M _A_1 M _A_2 M _A_3 IO_3V3 M _A_4 IO_GN D DIG_G ND M _A_5 DIG_1V8 M _A_6 M _A_7 M _A_8 M _A_9 M _A_10 IO_3V3 NV _CE_N M _WE_N IO_GN D M _CAS_N M _RAS_N M _BS0_N M _BS1_N M _AP M _CKE IO_3V3 M _CKO IO_GN D M _DQM _0 M _D_0 Figure 23. 240-Pin MQFP Pin Layout Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 7.2 240-Pin MQFP Pin Summary Figure 24 shows the pin names associated with each type of CS98200 interface. H _ D _ [1 5 : 0 ] H _ C S _ [3 :0 ] H _ A _ [3 :0 ] H_ALE H_RD H_W R H_RDY M _ A _ [1 0 : 0 ] M _B S 1_N M _B S 0_N M _ D _ [3 1 :0 ] M _ D Q M _ [3 :0 ] M _R AS _N M _C AS _N N V _ D [7 : 0 ] M _AP M _C K E M _C K O M _W E _N NV_CE_N H o s t M a s te r/ A T A P I (2 8 ) M e m o ry In te rfa c e (6 4 ) D V D _ D [7 : 0 ] D V D L o a d e r In te rfa c e (2 0 ) DVDL_RDY DVD_STB DVD_ENA DVD_SO S DVD_ERR DVD_RDY DVDL_DI DVDL_DO DVDL_CK CD_BCLK CD_LRCK C D _D ATA C D _C 2P O C S98200 V IN _ H S /V O U T _ H S V IN _ V S /V O U T _ V S V IN _ C L K / V O U T _ C L K V id e o In /O u t (1 1 ) V IN _ D [ 7 : 0 ] / V O U T _ D [7 : 0 ] A U D I_ B C K A U D I_ L R A U D I_ D _ [ 3 : 0 ] S P D IF _ O AUD_XCLK AU D O _B C K AU D O _LR A u d io O u t (8 ) A u d io In p u t (5 ) XTLCLO CK_I A U D O _ D _ [3 :0 ] M is c . (5 ) XTLCLO CK_O R S T_N IR _ IN TEST TX D _1 RXD_1 TX D _2 RXD_2 SCL1 SDA1 SCL2 SDA2 U A R T s (4 ) P o w e r/G n d : ( 6 8) I2 C D e b u g (4 ) Figure 24. 240-Pin MQFP Pinout Summary 7.3 Pin Configuration Summary The CS98200 has flexible pin functionality. Table 12 lists the different possible pin configurations and the settings required. The IO_Set value is programmed through a register, while the AUDO_D_0 and AUDO_LR values are set through pull up or pull down resistors on the pins. IO_Set[1:0] AUDO_D_0 AUDO_LR Host/ATAPI Pins Video In/Out Pins 00 00 00 01 01 01 10 10 10 11 11 11 1 0 0 1 0 0 1 0 0 1 0 0 X 0 1 X 0 1 X 0 1 X 0 1 Host master mode Video in mode Host slave mode Video in mode Host master mode Video in mode Host master mode Video out mode Host slave mode DVD mode Host slave mode DVD mode DVD mode Host slave mode DVD mode Video out mode Video in mode Video in mode Video in mode Video out mode Video out mode Video out mode Host master mode Video out mode DVD Pins DVD mode DVD mode Host slave mode Video in mode Video in mode Host slave mode GPIO mode GPIO mode Host slave mode Video in mode Video in mode Host slave mode Table 12. Pin Configuration Summary DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 37 CS98200 Next Generation DVD Processor 7.4 Explanation of Pin Types Table 13 lists the conventions used to identify the pin type and direction. Pin Type I IS ID IU O O4 O8 T4 B B4 B4U B8U B4S B4SU Pwr Gnd Name_N Input Input, with schmitt trigger Input, with pull down resistor Input, with pull up resistor Output Output - 4 mA drive Output - 8 mA drive High-Z Output - 4mA drive Bi-direction Bi-direction - 4 mA drive Bi-direction - 4 mA drive, with pull-up Bi-direction - 8 mA drive, with pull-up Bi-direction - 4 mA drive, with Schmitt trigger Bi-direction - 4 mA drive, with pull-up and Schmitt trigger +1.8 V or +3.3 V power supply voltage Power supply ground Low active Table 13. Pin Type Legen d Direction 7.5 240-Pin MQFP Pin Assignments Table 14 lists the pin number, pin name, and pin type for the 240-pin CS98200 package. The primary function and pin direction is shown for all signal pins. For some signal pins, a secondary function (or functions) and direction are also shown. For pins having more than one function, the primary function is chosen when the chip is reset. Pin # 1 2 3 4 5 6 7 8 9 10 Pin Name PLL_1V8 RST_N TEST IR_IN CDC_CLK CDC_SYNC CDC_SDO CDC_SDI IO_3V3 M_DQM_3 Type Pwr ISU I ISU B4S B4S B4S B4S Pwr B8 Primary Function PLL Power 1.8 V Reset Manufacturing Test IR in GPIO_MIS[18] GPIO_MIS[19] GPIO_MIS[20] GPIO_MIS[21] IO Power 3.3 V DRAM Byte_Enable[3] I I I Dir Secondary Function(s) Dir B B B B O Table 14. 240-Pin MQFP Pin Assignments 38 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor Pin # 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Pin Name M_D_31 M_D_30 M_D_29 IO_GND M_D_28 M_D_27 M_D_26 M_D_25 IO_3V3 M_D_24 M_D_23 DIG_1V8 M_D_22 DIG_GND IO_GND M_D_21 M_D_20 M_D_19 M_D_18 M_D_17 IO_3V3 M_D_16 M_DQM_2 IO_GND M_DQM_1 M_D_15 M_D_14 M_D_13 M_D_12 M_D_11 IO_3V3 Type B8 B8 B8 Gnd B8 B8 B8 B8 Pwr B8 B8 Pwr B8 Gnd Gnd B8 B8 B8 B8 B8 Pwr B8 B8 Gnd B8 B8 B8 B8 B8 B8 Pwr Primary Function DRAM Data[31] DRAM Data[30] DRAM Data[29] IO Ground DRAM Data[28] DRAM Data[27] DRAM Data[26] DRAM Data[25] IO Power 3.3 V DRAM Data[24] DRAM Data[23] Digital Power 1.8 V DRAM Data[22] Digital Ground IO Ground DRAM Data[21] DRAM Data[20] DRAM Data[19] DRAM Data[18] DRAM Data[17] IO Power 3.3 V DRAM Data[16] DRAM Byte_Enable[2] IO Ground DRAM Byte_Enable[1] DRAM Data[15] DRAM Data[14] DRAM Data[13] DRAM Data[12] DRAM Data[11] IO Power 3.3 V Dir B B B Secondary Function(s) Dir B B B B NVRAM Address[23] NVRAM Address[22] NVRAM Address[21] NVRAM Address[20] O O O O B B NVRAM Address[19] NVRAM Address[18] O O B NVRAM Address[17] O B B B B B NVRAM Address[16] NVRAM Address[15] NVRAM Address[14] NVRAM Address[13] NVRAM Address[12] O O O O O B O NVRAM Address[11] O O B B B B B Table 14. 240-Pin MQFP Pin Assignments (Continued) DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 39 CS98200 Next Generation DVD Processor Pin # 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Pin Name M_D_10 IO_GND DIG_GND M_D_9 DIG_1V8 M_D_8 M_D_7 M_D_6 M_D_5 M_D_4 IO_GND M_D_3 IO_3V3 M_D_2 M_D_1 VIN_D_0 Type B8 Gnd Gnd B8 Pwr B8 B8 B8 B8 B8 Gnd B8 Pwr B8 B8 B4 Primary Function DRAM Data[10] IO Ground Digital Ground DRAM Data[9] Digital Power 1.8 V DRAM Data[8] DRAM Data[7] DRAM Data[6] DRAM Data[5] DRAM Data[4] IO Ground DRAM Data[3] IO Power 3.3 V DRAM Data[2] DRAM Data[1] Primary Video_In Data[0] Dir B Secondary Function(s) Dir B B B B B B B B B I (1.) Secondary Video_Out Data[0] (2.) GPIO_VIS[0] (1.) Secondary Video_Out Data[1] (2.) GPIO_VIS[1] (1.) Secondary Video_Out Data[2] (2.) GPIO_VIS[2] (1.) Secondary Video_Out Data[3] (2.) GPIO_VIS[3] O B O B O B O B 58 VIN_D_1 B4 Primary Video_In Data[1] I 59 VIN_D_2 B4 Primary Video_In Data[2] I 60 61 62 63 64 65 66 67 68 69 70 VIN_D_3 M_D_0 M_DQM_0 IO_GND M_CKO IO_3V3 M_CKE M_AP M_BS1_N M_BS0_N M_RAS_N B4 B8 B8 Gnd O8 Pwr B8 B8 B8 B8 B8 Primary Video_In Data[3] DRAM Data[0] DRAM Byte_En[0] IO Ground DRAM Clock IO Power 3.3 V DRAM Clock Enable DRAM Auto Precharge DRAM BankSel[1] DRAM BankSel[0] DRAM Row Strobe I B O O Drc_Clock Eternal Input I O O O O O NVRAM_OE_N O Table 14. 240-Pin MQFP Pin Assignments (Continued) 40 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor Pin # 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 Pin Name M_CAS_N IO_GND M_WE_N NV_CE_N IO_3V3 M_A_10 M_A_9 M_A_8 M_A_7 M_A_6 DIG_1V8 M_A_5 DIG_GND IO_GND M_A_4 IO_3V3 M_A_3 M_A_2 M_A_1 M_A_0 NV_D_0 NV_D_1 NV_D_2 NV_D_3 NV_D_4 NV_D_5 IO_GND DIG_GND NV_D_6 DIG_1V8 NV_D_7 Type B8 Gnd B8 O4 Pwr B8 B8 B8 B8 B8 Pwr B8 Gnd Gnd B8 Pwr B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 Gnd Gnd B8 Pwr B8 Primary Function DRAM Col. Strobe IO Ground DRAM Write Enable ROM Chip Enable IO Power 3.3 V DRAM Address[10] DRAM Address[9] DRAM Address[8] DRAM Address[7] DRAM Address[6] Digital Power 1.8 V DRAM Address[5] Digital Ground IO Ground DRAM Address[4] IO Power 3.3 V DRAM Address[3] DRAM Address[2] DRAM Address[1] DRAM Address[0] NVRAM Data[0] NVRAM Data[1] NVRAM Data[2] NVRAM Data[3] NVRAM Data[4] NVRAM Data[5] IO Ground Digital Ground NVRAM Data[6] Digital Power 1.8 V NVRAM Data[7] Dir O Secondary Function(s) Dir O O NVRAM_WE_N O O O O O O NVRAM Address[10] NVRAM Address[9] NVRAM Address[8] NVRAM Address[7] NVRAM Address[6] O O O O O O NVRAM Address[5] O O NVRAM Address[4] O O O O O B B B B B B NVRAM Address[3] NVRAM Address[2] NVRAM Address[1] NVRAM Address[0] O O O O Table 14. 240-Pin MQFP Pin Assignments (Continued) DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 41 CS98200 Next Generation DVD Processor Pin # 102 Pin Name VIN_D_4 Type B4 Primary Function Primary Video_In Data[4] I Dir Secondary Function(s) (1.) Secondary Video_Out Data[4] (2.) GPIO_VIS[4] (1.) Secondary Video_Out Data[5] (2.) GPIO_VIS[5] (1.) Secondary Video_Out Data[6] (2.) GPIO_VIS[6] Dir O B O B O B 103 VIN_D_5 B4 Primary Video_In Data[5] I I 104 105 106 107 108 109 110 111 112 113 114 115 116 VIN_D_6 IO_3V3 VIN_D_7 SCL1 SDA1 SCL2 SDA2 TXD_1 RXD_1 TXD_2 RXD_2 PWM_O DVD_RDY B4 Pwr B4 B4SU B4SU B4SU B4SU B4 B4 B4 B4 B4 B4 Primary Video_In Data[6] IO Power 3.3 V Primary Video_In Data[7] I2C Debug Slave I2C Debug Slave I2C Master/Simple Slave I2C Master/Simple Slave UART1 Tx Data UART1 Rx Data UART2 Tx Data UART2 Rx Data PWM Output Prim. DVD Loader data Request I B B B B O I O I O O (1.) Secondary Video_Out Data[7] (2.) GPIO_VIS[7] O B GPIO_MIS[0] GPIO_MIS[1] GPIO_MIS[6] GPIO_MIS[7] GPIO_MIS[8] GPIO_MIS[9] GPIO_MIS[10] GPIO_DVD[12] (1.) Secondary Video_In Vsync (2.) GPIO_DVD[13] (3.) Secondary Host Slave Read (1.) Secondary Video_In Hsync (2.) GPIO_DVD[14] (3.) Secondary Host Slave Write (1.) Secondary Video_In Clock (2.) GPIO_DVD[15] (3.) Secondary Host Slave Ready B B B B B B B B I B I I B I I B O 117 DVDL_DI B4 Primary DVD Control Data In I 118 DVDL_DO B4 Primary DVD Control Data Out O 119 DVDL_CK B4S Primary DVD Control Clock O 120 121 122 PLL_1V8 PLL_GND IO_GND Pwr Gnd Gnd PLL Power 1.8 V PLL Ground IO Ground (1.) Secondary DVD Data[0] (2.) GPIO_HST[0] (3.) Primary Host Slave Data[0] (4.) Primary Video_Out Data[0] I B B O 123 H_D_0 B4 Host Master Data[0] B Table 14. 240-Pin MQFP Pin Assignments (Continued) 42 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor Pin # Pin Name Type Primary Function Dir Secondary Function(s) (1.) Secondary DVD Data[1] (2.) GPIO_HST[1] (3.) Primary Host Slave Data[1] (4.) Primary Video_Out Data[1] (1.) Secondary DVD Data[2] (2.) GPIO_HST[2] (3.) Primary Host Slave Data[2] (4.) Primary Video_Out Data[2] (1.) Secondary DVD Data[3] (2.) GPIO_HST[3] (3.) Primary Host Slave Data[3] (4.) Primary Video_Out Data[3] (1.) Secondary DVD Data[4] (2.) GPIO_HST[4] (3.) Primary Host Slave Data[4] (4.) Primary Video_Out Data[4] (1.) Secondary Video_Out Vsync (2.) GPIO_VIS[8] (3.) Host Master Chip Select[4] (1.) Secondary Video_Out Hsync (2.) GPIO_VIS[9] (3.) Host Master Chip Select[5] Dir I B B O I B B O I B B O I B B O O B O O B O 124 H_D_1 B4 Host Master Data[1] B 125 H_D_2 B4 Host Master Data[2] B 126 H_D_3 B4 Host Master Data[3] B 127 H_D_4 B4 Host Master Data[4] B 128 VIN_VS B4 Primary Video_In Vsync I 129 VIN_HS B4 Primary Video_In Hsync I 130 131 132 IO_3V3 VIN_CLK IO_GND Pwr B4S Gnd IO Power 3.3 V Primary Video_In Clock IO Ground (1.) Secondary DVD Data[5] (2.) GPIO_HST[5] (3.) Primary Host Slave Data[5] (4.) Primary Video_Out Data[5] (1.) Secondary DVD Data[6] (2.) GPIO_HST[6] (3.) Primary Host Slave Data[6] (4.) Primary Video_Out Data[6] (1.) Secondary DVD Data[7] (2.) GPIO_HST[7] (3.) Primary Host Slave Data[7] (4.) Primary Video_Out Data[7] (1.) Secondary DVD Control Clock (2.) GPIO_HST[8] (1.) Secondary DVD Control Ready (2.) GPIO_HST[9] (1.) Secondary DVD Control Data Out (2.) GPIO_HST[10] (1.) Secondary DVD Control Data In (2.) GPIO_HST[11] I B B O I B B O I B B O O B I B O B I B I (1.) Secondary Video_Out Clock (2.) GPIO_VIS[10] O B 133 H_D_5 B4 Host Master Data[5] B 134 H_D_6 B4 Host Master Data[6] B 135 H_D_7 B4 Host Master Data[7] B 136 H_D_8 B4 Host Master Data[8] B 137 H_D_9 B4 Host Master Data[9] B 138 H_D_10 B4 Host Master Data[10] B 139 H_D_11 B4 Host Master Data[11] B Table 14. 240-Pin MQFP Pin Assignments (Continued) DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 43 CS98200 Next Generation DVD Processor Pin # Pin Name Type Primary Function Dir Secondary Function(s) (1.) Secondary CD C2P0 (2.) GPIO_HST[12] (3.) Secondary DVDS_VLD (1.) Secondary CD_BCLK (2.) GPIO_HST[13] (3.) Secondary DVDS_CLK (1.) Secondary CD_LRLK (2.) GPIO_HST[14] (3.) Secondary DVDS_SOS (1.) Secondary CD_Data (2.) GPIO_HST[15] (3.) Secondary DVDS_DATA (1.) Primary DVDS_CLK (2.) GPIO_DVD[17] (3.) Secondary Host Slave Address[0] (1.) Primary DVDS_SOS (2.) GPIO_DVD[18] (3.) Secondary Host Slave Address[1] (1.) Primary DVDS_DATA (2.) GPIO_DVD[19] (3.) Secondary Host Slave Address[2] (1.) Primary DVDS_VLD (2.) GPIO_DVD[20] (3.) Secondary Host Slave Address[3] Dir I B I I B I I B I I B I I B I I B I I B I I B B 140 H_D_12 B4 Host Master Data[12] B 141 H_D_13 B4S Host Master Data[13] B 142 H_D_14 B4 Host Master Data[14] B 143 H_D_15 B4 Host Master Data[15] B 144 CD_BCLK B4S Primary CD Bit Clock I 145 CD_LRCK B4 Primary CD L/R Clock I 146 CD_DATA B4 Primary CD Data I 147 CD_C2P0 B4 Primary CD C2P0 I 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 DAC_AGND DAC_D1V8 DAC_DGND C_OUT DAC_A3V3 DAC_AGND Y_OUT DAC_A3V3 DAC_AGND CV_OUT DAC_A3V3 DAC_AGND COMP1 ISET1 VREF1 Gnd Pwr Gnd Anlg Pwr Gnd Anlg Pwr Gnd Anlg Pwr Gnd Anlg Anlg Anlg Analog Ground Digital Power 1.8 V Digital Ground C_OUT Analog Power 3.3 V Analog Ground Y_OUT Analog Power 3.3 V Analog Ground CV_OUT Analog Power 3.3 V Analog Ground Compensation Current Set Voltage Ref Table 14. 240-Pin MQFP Pin Assignments (Continued) 44 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor Pin # 163 164 165 166 167 168 169 170 171 172 Pin Name DAC_AGND DAC_A3V3 DAC_AGND DAC_A3V3 DAC_A3V3 DVDL_RDY DIG_1V8 H_A_0 DIG_GND H_A_1 Type Gnd Pwr Gnd Pwr Pwr B4 Pwr B4 Gnd B4 Primary Function Analog Ground Analog Power 3.3 V Analog Ground Analog Power 3.3 V Analog Power 3.3 V Primary DVD Control Ready Digital Power 1.8 V Host Master Address[0] Digital Ground Host Master Address[1] I Dir Secondary Function(s) Dir (1.)GPIO_DVD[16] (2.) Secondary Host Slave Chip_Select B I O (1.) GPIO_HST[16] (2.) Primary Host Slave Address[0] B I O (1.) GPIO_HST[17] (2.) Primary Host Slave Address[1] (1.) GPIO_HST[18] (2.) Primary Host Slave Address[2] (1.) Secondary Video_In Data[0] (2.) GPIO_DVD[0] (3.) Secondary Host Slave Data[0] (1.) Secondary Video_In Data[1] (2.) GPIO_DVD[1] (3.) Secondary Host Slave Data[1] (1.) GPIO_HST[19] (2.) Primary Host Slave Address[3] GPIO_HST[20] (1.) Secondary Video_In Data[2] (2.) GPIO_DVD[2] (3.) Secondary Host Slave Data[2] (1.) Secondary Video_In Data[3] (2.) GPIO_DVD[3] (3.) Secondary Host Slave Data[3] B I B I I B B I B B B I B I B B I B B 173 H_A_2 B4 Host Master Address[2] O 174 DVD_D_0 B4 Primary DVD Data[0] I 175 DVD_D_1 B4 Primary DVD Data[1] I 176 177 H_A_3 H_ALE B4 B4 Host Master Address[3] Host Master Address Latch O O 178 DVD_D_2 B4 Primary DVD Data[2] I 179 DVD_D_3 B4 Primary DVD Data[3] I 180 181 PLL_1V8 PLL_GND Pwr Gnd PLL Power 1.8 V PLL Ground (1.) Secondary Video_In Data[4] (2.) GPIO_DVD[4] (3.) Secondary Host Slave Data[4] (1.) Secondary Video_In Data[5] (2.) GPIO_DVD[5] (3.) Secondary Host Slave Data[5] I B B I B B 182 DVD_D_4 B4 Primary DVD Data[4] I 183 DVD_D_5 B4 Primary DVD Data[5] I Table 14. 240-Pin MQFP Pin Assignments (Continued) DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 45 CS98200 Next Generation DVD Processor Pin # Pin Name Type Primary Function Dir Secondary Function(s) (1.) Secondary Video_In Data[6] (2.) GPIO_DVD[6] (3.) Secondary Host Slave Data[6] (1.) Secondary Video_In Data[7] (2.) GPIO_DVD[7] (3.) Secondary Host Slave Data[7] (1.) Secondary DVD Start Sector (2.) GPIO_HST[21] (3.) Primary Host Slave Chip Select (1) Secondary DVD Error (2.) GPIO_HST[22] Dir I B B I B B I B I I B 184 DVD_D_6 B4 Primary DVD Data[6] I 185 DVD_D_7 B4 Primary DVD Data[7] I 186 H_CS_0 B4 Host Master Chip_Select[0] O 187 188 189 190 191 H_CS_1 IO_3V3 H_CS_2 IO_GND H_CS_3 B4 Pwr B4 Gnd B4 Host Master Chip_Select[1] IO Power 3.3 V Host Master Chip_Select[2] IO Ground Host Master Chip_Select[3] O O GPIO_HST[23] B O GPIO_HST[24] (1.) Secondary DVD Ready (2.) GPIO_HST[25] (3.) Primary Host Slave Read (1.) Secondary DVD Data Enable (2.) GPIO_HST[26] (3.) Primary Host Slave Write (1.) Secondary DVD Data Strobe (2.) GPIO_HST[27] (3.) Primary Host Slave Ready GPIO_MIS[2] GPIO_MIS[3] GPIO_MIS[4] GPIO_MIS[5] GPIO_MIS[15] GPIO_MIS[16] (1.) Aud_Pll_Aux_FIN[0] (2.) GPIO_MIS[17] (3.) AudioOut_Mute B O B I I B I I B O B B B O B B I B O 192 H_RD B4 Host Master Read O 193 H_WR B4 Host Master Write O 194 H_RDY B4S Host Master Ready I 195 196 197 198 199 200 SPI_CLK SPI_DO SPI_DI SPI_RDY AUDI_D AUDI_LR B4S B4 B4 B4 B4 B4 SPI Clock SPI Data Out/InOut SPI Data In SPI Ready / Chip Select PCM Input Data PCM LR Clock B B I B I I 201 AUDI_BCK B4S PCM Input Clock I 202 203 204 205 206 DAC_AGND DAC_D1V8 DAC_DGND UB_OUT DAC_A3V3 Gnd Pwr Gnd Anlg Pwr Analog Ground Digital Power 1.8 V Digital Ground UB_OUT_1 Analog Power 3.3 V Table 14. 240-Pin MQFP Pin Assignments (Continued) 46 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor Pin # 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 Pin Name DAC_AGND YG_OUT DAC_A3V3 DAC_AGND VR_OUT DAC_A3V3 DAC_AGND COMP2 ISET2 VREF2 DAC_AGND DAC_A3V3 DAC_AGND DAC_A3V3 DAC_A3V3 AUDO_LR DIG_1V8 AUDO_BCK DIG_GND AUD_XCLK AUDO_D_1 Type Gnd Anlg Pwr Gnd Anlg Pwr Gnd Anlg Anlg Anlg Gnd Pwr Gnd Pwr Pwr B4 Pwr B4 Gnd B4S B4 Primary Function Analog Ground YG_OUT_1 Analog Power 3.3 V Analog Ground VR_OUT_1 Analog Power 3.3 V Analog Ground Compensation Current Set Voltage Ref Analog Ground Analog Power 3.3 V Analog Ground Analog Power 3.3 V Analog Power 3.3 V PCM LR Clock Digital Power 1.8 V PCMO BCLK Digital Ground PCM MCLK Output PCM Data Out[1] Dir Secondary Function(s) Dir O (1.) Clock_Monitor_CPU (2.) Host ParSlave_Set O I O (1.) Clock_Monitor_DRC (2.) GPIO_MIS[11] O B O O PCM MCLK External Input (1.) System Clock External Input (2.) GPIO_MIS[12] (1.) CPU clock External Input (2.) GPIO_MIS[13] (1.) Aud_PLL_AUX_FIN[1] (2.) GPIO_MIS[14] I I B I B I B 228 AUDO_D_2 B4 PCM Data Out[2] O 229 230 231 232 233 234 AUDO_D_3 IO_3V3 XTLCLK_I XTLCLK_O IO_GND AUDO_D_0 B4 Pwr OSC OSC Gnd B4 PCM Data Out[3] IO Power 3.3 V 27 MHz Clock In 27 MHz Clock Out IO Ground PCM Data Out[0] O I O O (1.) Main_Clock_Monitor (2.) HostSlave_Par_I2C_Sel O I Table 14. 240-Pin MQFP Pin Assignments (Continued) DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 47 CS98200 Next Generation DVD Processor Pin # 235 236 Pin Name SPDIF_O DVD_STB Type B4 B4S Primary Function SPDIF Primary DVD Data Strobe Dir O I Secondary Function(s) Process_Monitor_Out (1.) Host Master Address[4] (2.) GPIO_DVD[8] (1.) Host Master Address[5] (2.) GPIO_DVD[9] (1.) Host Master Address[6] (2.) GPIO_DVD[10] (1.) Host Master Address[7] (2.) GPIO_DVD[11] Dir O O B O B O B O B 237 DVD_ENA B4 Primary DVD Data Enable I 238 DVD_SOS B4 Primary DVD Start Sector I 239 240 DVD_ERR PLL_GND B4 Gnd Primary DVD Error PLL Ground I Table 14. 240-Pin MQFP Pin Assignments (Continued) 48 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 8. INTERFACE DESCRIPTIONS 8.1 SDRAM Interface Pins These pins are used to interface the CS98200 with some external SDRAM. The CS98200 can interface with SDRAM of various sizes. Only 32-bit data width is supported. Follow the instructions in Table 15 on how to interface with any particular configuration of SDRAM. Pin 11,12,13,15,16, 17,18,20,21,23, 26,27,28,29,30, 32,61, 56, 55, 53, 51, 50, 49, 48, 47, 45, 42, 40, 39, 38, 37, 36, 90, 89, 88, 87, 85, 82, 80, 79, 78, 77, 76 64 66 69 68 67 70 71 73 62, 35, 33, 10 Signal Name M_D[31:0] Type B Description Memory Data Bus. CS98200 uses all 32 bits. M_A[10:0] O Memory Address Bus. Connect in order starting with M_A[0] to all RAM address pins not already connected to M_BS[1:0]_N or M_AP. Memory Clock Memory Clock Enable Bank Selection. Always connect to RAM BS or BS0 pin. Bank Selection. Always connect to RAM BS or BS0 pin. Memory Auto Pre-charge. Always connect to RAM AP pin. Memory Row Address Strobe Memory Column Address Strobe Memory Write Enable IO Mask of Data Bus M_DQM[3] -> M_D[31:24] M_CKO M_CKE M_BS0_N M_BS1_N M_AP M_RAS_N M_CAS_N M_WE_N M_DQM[3:0] O O O O O O O O O Table 15. SDRAM Interface Pins 8.2 ROM/NVRAM Interface Pins This is the interface to the non-volatile memory that contains the firmware. See Table 16. It could be either ROM, NVRAM - FLASH, or EEPROM, or any combination of these types of memory. This interface can also connect to SRAM that would emulate a ROM on a development system. The bus width is 8 bits. Pin 91,92,93,94,95, 96,99,101 90, 89, 88, 87, 85, 82, 80, 79, 78, 77, 76 32, 30, 29, 28, 27, 26, 23, 21, 20, 18, 17, 16 67 73 Signal Name NV_D[7:0] M_A[10:0] Type B O Memory Data Bus. Memory Address Bus[10:0] Description M_D[31:16] O Memory Address Bus[23:11] M_AP M_WE_N O O Output Enable Write Enable. Table 16. ROM/NVRAM Interfa c e DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 49 CS98200 Next Generation DVD Processor 74 NV_CE_N O ROM/NVRAM Chip Enable. Table 16. ROM/NVRAM Interface (Continued) 8.3 Video Output Interface Pins This is the interface to a video encoder chip that will send the CS98200 video signals to a TV. See Table 17. This interface uses the same pins of the Video Input Interface, so you are not able to use Video Input (primary) and Video Output (Secondary) at the same time. . Pin 131s 129s 128s 57s, 58s, 59s, 60s, 102s, 103s, 104s, 106s Signal Name VOUT_CLK VOUT_HS VOUT_VS VOUT_D[7:0] Type O O O O 27 Mhz Clock Output. Horizontal Sync. Output when the CS98200 is the video master, input when the video encoder is master. Vertical Sync. Output when the CS98200 is the video master, input when the video encoder is master. Video Data Output[7:0] in Cb, Y, Cr, Y format. Description Table 17. Video Output Interface 8.4 Video Input Interface Pins See Table 18. Pin 131 128 129 57, 58, 59, 60, 102, 103, 104, 106 Signal Name VIN_CLK VIN_VS VIN_HS VIN_D [7:0] Type I I I I Video Input Clock. Video Input Vertical Sync. Video Input Horizontal Sync. Video Data Input[7:0] in Cb, Y, Cr, Y format. Description Table 18. Video Input Interface 50 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 8.5 Audio PCM Interface Pins This is the audio PCM interface that connects to an audio CODEC. See Table 19. The sample rate and the size of the samples are programmable for both input and output direction. Pin 226 224 222 234 227 228 229 235 201 Signal Name AUD_XCLK AUDO_BCK AUDO_LR AUDO_D_0 AUDO_D_1 AUDO_D_2 AUDO_D_3 SPDIF_O AUDI_BCK Type B O O O O O O O I Description Audio 256x/384x Clock input or output to Serial DAC. When output, is generated from CS98200 internal PLL. Audio Bit Clock output to serial DAC. Audio Out Left/Right Clock to serial DAC. Audio Serial Data Out[0]. Audio Serial Data Out[1]. Audio Serial Data Out[2]. Audio Serial Data Out[3]. S/PDIF Output Audio Input Bit Clock. The CS98200 can be programmed to use the Audio Output function's internally generated bit clock, in which case this pin is not required. Audio Input Left/Right Clock. The CS98200 can be programmed to use the Audio Output function's internally generated LR clock, in which case this pin is not required. Audio Input Data from Serial ADC. 200 AUDI_LR I 199 AUDI_D I Table 19. PCM Audio Interfa c e DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 51 CS98200 Next Generation DVD Processor 8.6 Host Master/ATAPI Interface Pin Signal Name H_CS[3:0] Type O Description Host Chip Select[3:0]. The host master can be programmed to use a different protocol for each of the 4 chip selects Host address latch enable. Used for modes which multiplex upper address information onto the data lines Host Read Request. Host Write Request. Host Ready. Connect to pull-up or pull-down if host is not used. Host Address[3:0]. Host Data Bus[15:0]. These pins can also output Host Address during the address phase for multiplexed address/data mode. Tie together to pull-up or pull-down if host is not used. 186, 187, 189, 191 177 H_ALE O 192 193 194 170, 172, 173, 176 123, 124, 126, 127, 134, 135, 137, 138, 140, 141, 143 125, 133, 136, 139, 142, H_RD H_WR H_RDY H_A[3:0] H_D[15:0] O O I O B Table 20. Host Master/ATAPI Interface 52 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 8.7 DVD Loader Interface This interface connects to standard DVD loaders, and consists of three parts: Control, DVD Data and CD Data. (See Table 21.) This interface shares CS98200 pins with the Host Master/ATAPI interface. (See Table 20 on page 52.) The definition of the pins is set via register programming, and the two modes are mutually exclusive. Pin 174, 175, 178, 179, 182, 183, 184, 185 168 236 237 238 239 116 117 118 119 144 145 146 147 Signal Name DVD_D[7:0] Type I Primary DVD Data Description DVDL_RDY DVD_STB DVD_ENA DVD_SOS DVD_ERR DVD_RDY DVDL_DI DVDL_DO DVDL_CK CD_BCLK CD_LRCK CD_DATA CD_C2PO I I I I I O I O O I I I I Primary DVD Control Ready Primary DVD Data Strobe Primary DVD Data Enable Primary DVD Start Sector Primary DVD Error Primary DVD Data Request Primary DVD Control Data In Primary DVD Control Data Out Primary DVD Control Clock Primary CD Bit Clock Primary CD L/R Clock Primary CD Data Primary CD C2P0 Table 21. DVD I/O Channel Interface 8.8 DVD Serial Data Interface This interface connects to the data port of low cost DVD loaders using a 4-wire serial interface. In this case, control for the loader will typically be done using the 2-wire serial interface master. The ATAPI/IO channel pins are then free to be used for a second DVD loader, a general purpose ATAPI, or as GPIOs. Pin 144s /141s 146s/143s 147s/140s 145s/142s Signal Name DVDS_CLK DVDS_DATA DVDS_VLD DVDS_SOS Type I I I I DVD Clock Input DVD serial data input (data can be input MSB or LSB first) DVD valid ( a bit of data is clocked in when this pin is high) DVD start of sector input Description DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 53 CS98200 Next Generation DVD Processor 8.9 SPI Interface The SPI Interface supports industry standard 3-wire protocols. (See Table 22) In master mode, this interface can control a front panel or a small non-volatile memory. In slave mode, it can operate under control of an external processor, for example, in a combination unit. Pin 195 196 197 198 Signal Name SPI_CLK SPI_DO SPI_DI SPI_RDY Type B B I B SPI Clock SPI Data In/Out SPI Data In SPI Ready / Chip Select Description Table 22. SPI Interface 8.10 General Purpose Input/Output (GPIO) The CS98200 provides enough GPIO pins, each with individual output High-Z-state controls. HighZ-state means that the output driver is turned off or placed in the high-impedance state. Table 23 describes the General Purpose I/O Interface. Additional pins may also be re-defined as GPIOs. Pin 174s, 175s, 178s, 179s, 182s, 183s, 184s, 185s, 236s, 237s, 238s, 239s, 116s, 117s, 118s, 119s, 168s, 144s, 145s, 146s, 147s, 123s, 124s, 125s, 126s, 127s, 133s, 134s, 135s, 136s, 137s, 138s, 139s, 140s, 141s, 142s, 143s, 170s, 172s, 173s, 176s, 177s, 186s, 187s, 189s, 191s, 192s, 193s, 194s 57s, 58s, 59s, 60s, 102s, 103s, 104s, 106s, 128s, 129s, 131s, 109s, 110s, 125s, 126s, 127s, 198s, 111s, 112s, 113s, 114s, 115s, 224s, 227s, 228s, 229s, 199s, 200s, 201s, 5s, 6s, 7s, 8s Signal Name GPIO_DVD[20:0] Type B Description 21 General purpose I/Os GPIO_HST[0:27] B 28 General purpose I/Os GPIO_VIS[0:10] B 11 General purpose I/Os GPIO_MIS[0:21] B 22 General purpose I/Os Table 23. General Purpose I/O Interface 54 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 8.11 UART Interface Pins The CS98200 has two 16550-type UARTs for RS-232 serial communications, both of which have two 16-byte FIFOs for receiving and transmitting data. Pin 111 112 113 114 Signal Name TXD_1 RXD_1 TXD_2 RXD_2 Type O I O I UART1 Tx Data UART1 Rx Data UART2 Tx Data UART2 Rx Data Description Table 24. UART Interface Pins 8.12 I2C Interface The I2C pins are used for both master and slave mode. Pin 107 108 109 110 Signal Name SCL1 SDA1 SCL2 SDA2 Type B B B B I2C Debug Slave I2C Debug Slave I2C Master/Simple Slave I2C Master/Simple Slave Description Table 25. I2C Interface Pins 8.13 Miscellaneous Interface Pins These pins are used for used for basic functions such as clock and reset input. See Table 26. Pin 4 231 232 2 3 Signal Name IR_IN XTLCLK_I XTLCLK_O RST_N TEST Type I I O I I 27 MHz Clock Input. 27 MHz Clock Output. Reset Input, active low. Manufacturing test pin, should always connect to ground. Description Infrared Input, from IR receiver. Table 26. Miscellaneous Interface Pins DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 55 CS98200 Next Generation DVD Processor 8.14 Power and Ground The CS98200 requires 4 different types of power supplies - PLLs, digital, analog, and IO pins -. The PLLs and digital power use 1.8 V power supply. The IO pins and digital power use 3.3 V power supply, and are 5 V input tolerant. (See Table 27.) Pin 1, 120, 180, 149, 203 152, 155, 164, 166, 206, 209, 218, 220, 158, 167, 212, 221 Signal Name PLL_1V8 DAC_D1V8 DAC_A3V3 Type 2.5 V for internal PLLs Digital Power 1.8 V Analog Power 3.3 V Description 9, 19, 31, 41, 54, 65, 75,86, 105, 130, 188, 230 22,46, 81, 100, 169, 223 150, 204 148,153, 156, 159, 163, 165, 202, 207, 210, 213, 217, 219 121, 181, 240 14, 25, 34, 43, 52, 63, 72, 84, 97, 122, 132, 190, 233 24, 44, 83, 98, 171, 225 IO_3V3 3.3 V for I/Os DIG_1V8 DAC_DGND DAC_AGND Digital Power Digital Ground Analog Ground PLL_GND IO_GND Ground for internal PLLs Ground for I/Os DIG_GND Digital Ground Table 27. Power and Ground 56 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 9. 240-PIN MQFP PACKAGE SPECIFICATIONS 34.35 34.85 31.90 32.10 0.10 0.30 31.90 32.10 34.35 34.85 0.50 TYP Pin 1 Indicator Pin 240 Pin 1 0.40 0.60 3.20 3.60 0.16 TYP 4.10 MAX 0.25 MIN 0 MIN 7 MAX NOTES: 1) Dimensions are in millimeters, and controlling dimension is millimeter. 2) Package body dimensions do not include mold protrusion, which is 0.25 mm (0.010 in). 3) Pin 1 identication may be either ink dot or dimple. 4) Package top dimensions can be smaller than bottom dimensions by 0.20 mm (0.008 in). 5) The Olead width with platingO dimension does not include a total allow le dambar protrusion of 0.08 mm ab (at maximum material condition). 6) Ejector pin marks in molding are present on every package. 7) Drawing above does not reect exact package pin count. Figure 25. 240-Pin MQFP Package Drawing DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 57 CS98200 Next Generation DVD Processor 10. CONVENTIONS This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. 10.1 Acronyms and Abbreviations Table 28 lists abbreviations and acronyms used in this data sheet. Acronym/ Abbreviation A/D ADC CODEC D/A DMA EPB FCS FIFO FIQ GPIO ICT IR IRQ IrDA JTAG LCD LED MQFP LSB MIPS MMU MSB PBGA PCB PDA PLL p/u RISC RTC SIR SRAM SSI Definition analog-to-digital analog-to-digital converter coder / decoder digital-to-analog direct-memory access embedded peripheral bus frame check sequence first in / first out fast interrupt request general purpose I/O in circuit test infrared standard interrupt request Infrared Data Association Joint Test Action Group liquid crystal display light-emitting diode Medium profile quad flat pack least significant bit millions of instructions per second memory management unit most significant bit plastic ball grid array printed circuit board personal digital assistant phase locked loop pull-up resistor reduced instruction set computer Real-Time Clock slow (9600-115.2 kbps) infrared static random access memory synchronous serial interface Table 28. Acronyms and Abbreviatio ns 58 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor Acronym/ Abbreviation TAP TLB UART Definition test access port translation lookaside buffer universal asynchronous receiver Table 28. Acronyms and Abbreviations (Continued) 10.2 Units of Measurement Symbol Unit of Measure degree Celsius sample frequency hertz (cycle per second) kilobits per second kilobyte (1,024 bytes) kilohertz kilo Ohm megabits (1,048,576 bits) per second megabyte (1,048,576 bytes) megabytes per second megahertz (1,000 kilohertz) microampere microfarad microwatt microsecond (1,000 nanoseconds) milliampere milliwatt millisecond (1,000 microseconds) nanosecond volt watt C fs Hz kbps KB kHz k Mbps MB MBps MHz A F W s mA mW ms ns V W Table 29. Units of Measurement 10.3 General Conventions Hexadecimal numbers are presented with all letters in uppercase and a lowercase "h" appended or with a 0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text (for example, `11' designates a binary number). Numbers not indicated by an "h", 0x or quotation marks are decimal. Registers are referred to by acronym, with bits listed in brackets separated by a colon (:) (for example, CODR[7:0]), and are described in the CS98200 Registers document. The use of "TBD" indicates values that are "to be determined," "n/a" designates "not available," and "n/c" indicates a pin that is a "no connect." DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 59 CS98200 Next Generation DVD Processor 10.4 Pin Description Conventions Abbreviations used for signal directions are listed in Table 30. Pin numbers that have an "s" after the pin number indicate that the pin is using a secondary function for that pin. Abbreviation I O B Input Output Input or Output Direction Table 30. Pin Description Conventions 11. ORDERING INFORMATION LEGEND Here is the legend for understanding the ordering information listed above. CS98200 -- CV --XX Processor Speed Package Type: V = Low Profile Quad Flat Pack (240-pin LQFP) B = Plastic Ball Grid Array (17 mm x 17 mm) (256-ball PBGA) M = Medium Profile Quad Flat Pack (240-pin MQFP) R = Reduced Ball Grid Array (13 mm x 13 mm) (204-pin TFBGA) Part Number Product Line: Embedded Processor Temperature Range: C = Commercial E = Extended Operating Version I = Industrial Operating Version Note: Go to the Cirrus Logic Internet site at http://cirrus.com/corporate/contacts to find contact information for your local sales representative. 60 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 |
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